The present invention relates to semiconductor devices, such as MOS-type field effect transistors (hereinafter referred to as “MOSFETs”) and insulated-gate bipolar transistors (hereinafter referred to as “IGBTs”), that have a gate structure formed of a metal (M), an oxide film (O), and a semiconductor layer (S). Specifically, the present invention relates to vertical semiconductor devices that exhibit a high breakdown voltage and low loss, include electrodes on the major surfaces of a semiconductor chip, and having current flow vertically between the electrodes.
Vertical semiconductor devices typically have current flow between the electrodes on the major surfaces of a semiconductor chip and are used widely as power semiconductor devices. FIG. 31 is a cross-sectional view of the active region of a conventional planar-type n-channel vertical MOSFET, which have main current flow in a vertical direction. The conventional vertical MOSFET shown in FIG. 31 includes a metal drain electrode 20, an n+-type drain layer 11 having a low electrical resistance in electrical contact with the drain electrode 20, an n−-type drift layer 12 working as a layer for sustaining a voltage on the n+-type drain layer 11, p-type well regions 13 formed selectively in the surface portion of the n−-type drift layer 12, and an n+-type source region 15 formed selectively in the surface portion of p-type well regions 13.
A gate electrode 18 is above the extended portion of the p-type well region 13, which extends between the n+-type source regions 15, and the extended portion 14 of the drift layer 12, which extends between the p-type well regions 13, with a gate insulation film 17 interposed therebetween. Hereinafter, the extended portion 14 of the drift layer 12 will be referred to as the “surface drain region” or as the “n−-type surface region.” A source electrode 19 is in contact commonly with the n+-type source regions 15 and the p-type well regions 13. A p+-type contact region 21 is formed in the surface portion of the p-type well region 13. The p+-type contact region 21 is in contact with the source electrode 19 to reduce the contact resistance between the p-type well region 13 and the source electrode 19, or to improve the latch-up withstanding capability.
Although it is possible to express the on-resistance in the ON-state of the vertical MOSFET by the total resistance of the current path inside the device, the resistance of the very resistive n−-type drift layer 12 occupies the most part of the total resistance of the semiconductor device, exhibiting a high breakdown voltage. For reducing the losses of the MOSFET, it is effective to reduce the specific resistance or thickness of the n−-type drift layer 12. However, since the n−-type drift layer 12 is depleted in the OFF-state of the device such that the n−-type drift layer 12 sustains the voltage, heavily doping or thinning the n−-type drift layer 12 to reduce the specific resistance thereof undesirably reduces the breakdown voltage. On the other hand, thickening the n−-type drift layer 12 to obtain a semiconductor device with a high breakdown voltage inevitably causes high on-resistance and high losses. In short, there exists a tradeoff relation between the on-resistance and the breakdown voltage. It is well known that the tradeoff relation between the on-resistance and the breakdown voltage exists not only in the MOSFETs but also in the other power semiconductor devices such as IGBTs, bipolar transistors and diodes, although their degree is different from device to device.
Since the p-type well regions 13 are formed in the conventional semiconductor devices described above usually by introducing impurity ions through the gate electrode layer 18, which is used as a mask, the planar pattern of the p-type well regions 13 is an inversion of the planar pattern of the gate electrode layer 18. FIG. 32 is a top plan view showing a planar arrangement pattern of the gate electrode of the conventional n-channel vertical MOSFET. FIG. 33 is a top plan view showing another planar arrangement pattern of the gate electrode of the conventional n-channel vertical MOSFET.
Referring now to FIG. 32, the gate electrode 18 has square windows, as disclosed for example in Japanese Examined Patent Application H07 (1995)-83123. The p-type well regions 13 are square since the p-type well regions 13 are formed by introducing impurity ions through the square windows of gate electrode 18. The n+-type source region is shaped with a square ring since the n+-type source region is formed by introducing impurity ions through the window of the gate electrode 18 used for defining the sides of the n+-type source region. In FIG. 32, the contact regions 24 of the source electrode, formed in contact with the p-type well regions 13 and the n+-type source regions, are shown in the windows of the gate electrode. The contact region 24 has a square shape similar to that of the p-type well region 13.
Referring now to FIG. 33, the gate electrode 18 has hexagonal windows, as disclosed for example in U.S. Pat. No. 4,593,302. In this case, the p-type well regions 13 are hexagonal and the contact region 24 of the source electrode has a hexagonal shape similar to that of the p-type well region 13.
The MOS semiconductor devices also include a breakdown withstanding structure formed usually around the active region thereof to sustain the breakdown voltage of the devices. A guard ring structure, a field plate structure, or a combination of a resistive film and a field plate structure is employed for the breakdown withstanding structure.
However, the breakdown withstanding structures described above have realized 90% or less of the ideal breakdown voltage calculated from the semiconductor substrate used and the breakdown withstanding structure employed. For realizing the target breakdown voltage, it is desirable to use a semiconductor substrate having a high resistivity, a thick semiconductor substrate, or to employ a breakdown withstanding structure having sufficient leeway. Using such a structure, however, inevitably introduces high on-resistance even when the semiconductor devices require low on-resistance.
High on-resistance is inevitable due to the high resistivity in the main portion of the semiconductor substrate or to the thick semiconductor substrates employed. The resistivity ρ (Ωcm) of the main portion of the n-type drift layer 12 below the p-type well region 13 in the crystals used conventionally is expressed in terms of the breakdown voltage Vbr (V) of the MOSFET as follows:−8.89+0.0526 Vbr<ρ<−11.86+0.0702 Vbr.Only 90% or less of the ideal breakdown voltage calculated based on the structure of the semiconductor device is obtained because of 1) the planar arrangement of the active region and 2) the unoptimized breakdown withstanding structure, which breaks down in advance of the active region.
First, the problem of the conventional active region is described. When the shape of the p-type well region 13 is that shown in FIG. 32 or 33, the shape of each p-type well region 13 is defined by the surrounding n−-type surface regions 14 of the n−-type drift layer 12. In other words, the p-type well regions 13 are convex with respect to the n−-type surface regions 14. Due to the convex shape of the p-type well regions 13, the electric field strength across the pn-junction between the p-type well region 13 and the n−-type surface regions 14 is high. Due to the high electric field strength, the breakdown voltage in the pn-junction region is lower than the breakdown voltage determined by the impurity concentrations in the n−-type drift layer 12 and the p-type well region 13.
To avoid the problem described above, it has been necessary to dope the n−-type drift layer 12 lightly. The lightly doped n−-type drift layer 12, however, causes high on-resistance. To prevent the low breakdown voltage caused by the shape effect of the p-type well regions 13, U.S. Pat. No. 5,723,890 discloses a gate electrode, having its main portion formed of a plurality of stripes extending in one direction.
FIG. 34 is a top plan view showing the planar arrangement pattern of the gate electrode 18 disclosed in U.S. Pat. No. 5,723,890. In FIG. 34, the main portion of the p-type well region 13 is stripe shaped. The contact region 24 is also stripe shaped. However, the MOSFET having such striped gate electrode 18 is not completely free of the above noted problems.
The resistance of the gate electrode having square widows or hexagonal windows is suppressed at a low value since the control signal flows through the gate electrode, which works like a network due its shape. The resistance of the gate electrode formed of a plurality of stripes is still sufficiently high as to cause the switching loss increase, which is described later, since the control signal flows only in one direction from the ends of the stripes.
To reduce the losses of the MOSFET, it is desirable to reduce the switching loss, as well as to reduce the loss caused by the on-resistance in the ON-state of the device. Generally describing, to reduce the switching loss, it is important to shorten the switching time in which the device turns from the ON-state to the OFF-state. To shorten the switching time of the vertical MOSFET shown in FIG. 31, it is desirable to reduce the capacitance Crss between the n−-type surface region 14 and the gate electrode 18 facing the n−-type surface region 14 across the gate insulation film 17. To reduce the capacitance Crss, it is effective to narrow the width of the n−-type surface region 14 between the p-type well regions 13. Narrowing the width of the n−-type surface region 14, between the p-type well regions 13, however, increases the high resistance due to the effect of the junction-type field-effect transistor (hereinafter referred to as “JFET resistance”), which is one of the on-resistance components of the MOSFETs. The high JFET resistance increases the high on-resistance.
U.S. Pat. No. 4,593,302 discloses a counter doping method, which obviates the problem of high JFET resistance. Although the counter doping technique can suppress the JFET resistance increase, widening the width of the n−-type surface region 14, to reduce the JFET resistance, lowers the breakdown voltage. To avoid the breakdown voltage lowering, it is desirable to reduce the amount of the counter doped impurity. The reduced amount of the counter doped impurity is less effective to prevent the JFET resistance from increasing. Thus, all of the conventional techniques that solve one problem, fails to solve another problem, or initiates another problem.
To reduce the switching loss, it is effective to reduce the gate driving charge quantity Qg, as well as to reduce the capacitance Crss. The gate driving charge quantity Qg is calculated by the following expression (1), which calculates the charge quantity, charged to the input capacitance Ciss of the MOS-type semiconductor device from 0 V to the driving voltage V1 (V) of the voltage between the gate and the source Vgs:                     Qg        =                              ∫            0            V1                    ⁢                      Ciss            ×            Vgs            ⁢                                                   ⁢                                          ⅆ                C                            /                              ⅆ                V                                                                        (        1        )            The expression (1) indicates that the reduction of the input capacitance Ciss results in reduction of the gate driving charge quantity Qg.
The input capacitance Ciss of the MOS-type device is expressed by the following expression (2), including the capacitance between the terminals:Ciss=Cgs+Cgd  (2)Here, Cgs is the capacitance between the gate and the source, and Cgd is the capacitance between the gate and the drain (that is Crss).
In addition to the foregoing JFET resistance reduction that employs counter doping, there is another conventional way of reducing the capacitance Crss. FIG. 35 is a cross sectional view of another conventional n-channel vertical MOSFET, which reduces the capacitance Crss. Referring now to FIG. 35, the n-channel vertical MOSFET includes a thick gate insulation film 25 disposed on a part of the gate insulation film 17 facing the n−-type surface region 14 to reduce the capacitance Crss. Since steps are formed between gate insulation film 17 and the thick gate insulation films 25, however, the electric field strength in the step portions is high. The high electric field strength decreases the breakdown voltage.
Although narrowing the area of gate electrode 18 may be effective to reduce the capacitance Cgs between the gate and the drain, narrowing the width of the stripe-shaped gate electrode, for example, shown in FIG. 34, increases the gate resistance inside the device, increasing the switching loss.
Regarding the breakdown withstanding structure, since the pn-junction between the p-type well region 13 and the n−-type drift layer 12 has a curvature in the outermost peripheral portion of the p-type well region 13 at the same potential as that of the source electrode 19 on the n−-type drift layer 12, which acts as a breakdown-voltage sustaining layer, the electric field strength in the curved pn-junction rises more quickly than the electric field strength in the straight pn-junction. The electric field strength in the curved pn-junction reaches the critical electric field strength at a voltage lower than the breakdown voltage calculated from the structure of the breakdown-voltage sustaining layer, causing a breakdown.
In view of the foregoing, there is a need for a semiconductor device that exhibits a high breakdown voltage and greatly reduces the tradeoff relation between the on-resistance and the breakdown voltage, and reduces both the on-resistance and the switching loss.